`include "macro.v"
module PC (
    input wire clk,
    input wire rst_n,
    input wire pause,
    input wire pc_op_i,
    input wire [31:0] npc_i,

    output reg [31:0] pc_o,
    output wire [31:0] pc4_o
);

assign pc4_o = pc_o + 4;

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        pc_o <= 'b0;
    end else if (pc_op_i == `PC_NPC) begin
        pc_o <= npc_i;
    end else if (pause) begin
        pc_o <= pc_o;
    end else if (pc_op_i == `PC_PC4)begin
        pc_o <= pc4_o;
    end else begin
        pc_o <= 'b0;
    end
end
endmodule